
7
LTC1279
PI FU CTIO S
UU
U
AIN (Pin 1): Analog Input. 0V to 5V (Unipolar), ±2.5V
(Bipolar).
VREF (Pin 2): 2.42V Reference Output. Bypass to AGND
(10
F tantalum in parallel with 0.1F ceramic).
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 11 to 4): Three-State Data Outputs.
D11 is the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
DVDD (Pin17): Digital Power Supply, 5V. Tie to AVDD pin.
SHDN (Pin 18): Power Shutdown. The LTC1279 pow-
ers down when SHDN is low.
CONVST (Pin 19): Conversion Start Input. It is active
low. The falling edge of the CONVST signal initiates a
conversion. The LTC1279 responds to CONVST signal
only if the signal applied to CS is a logic low.
RD (Pin 20): READ Input. A logic low signal applied to
this pin enables the output data drivers when the signal
applied to the CS pin is a logic low.
CS (Pin 21): The CHIP SELECT input must be a logic low
for the ADC to recognize the signals applied to the
CONVST and RD inputs.
BUSY (Pin 22): The BUSY output shows the converter
status. It is a logic low during a conversion.
VSS (Pin 23): Negative Supply. – 5V will select bipolar
operation. Bypass to AGND with 0.1
F ceramic. Tie to
analog ground to select unipolar operation.
AVDD (Pin 24): Positive Supply, 5V. Bypass to AGND
(10
F tantalum in parallel with 0.1F ceramic).
FU CTIO AL BLOCK DIAGRA
UU
W
12-BIT CAPACITIVE DAC
COMPAR-
ATOR
2.42V REF
VREF
CSAMPLE
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
D11
D0
BUSY
CONTROL LOGIC
CS
CONVST
RD
SHDN
INTERNAL
CLOCK
ZEROING
SWITCH
DVDD
VSS
AVDD
(0V FOR UNIPOLAR MODE
OR –5V FOR BIPOLAR MODE)
AIN
AGND
DGND
12
1279 BD